ATTINY13A-MMUR Atmel, ATTINY13A-MMUR Datasheet - Page 51
![MCU AVR 1KB FLASH 20MHZ 10QFN](/photos/12/13/121304/313-10m1_sml.jpg)
ATTINY13A-MMUR
Manufacturer Part Number
ATTINY13A-MMUR
Description
MCU AVR 1KB FLASH 20MHZ 10QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-MMUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY13A-MMUR
Manufacturer:
TI
Quantity:
4 430
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10.2.2
10.2.3
10.2.4
8126E–AVR–07/10
Toggling the Pin
Switching Between Input and Output
Reading the Pin Value
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b10) as an intermediate step.
Table 10-1
Table 10-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
page 52
value. The maximum and minimum propagation delays are denoted t
respectively.
DDxn
0
0
0
1
1
shows a timing diagram of the synchronization when reading an externally applied pin
PORTxn
summarizes the control signals for the pin value.
0
1
1
0
1
Port Pin Configurations
(in MCUCR)
PUD
X
X
X
0
1
Figure 10-2 on page
Output
Output
Input
Input
Input
I/O
Pull-up
Yes
No
No
No
No
50, the PINxn Register bit and the preced-
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
pd,max
Figure 10-3 on
and t
pd,min
51
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