ATTINY45-20SUR Atmel, ATTINY45-20SUR Datasheet - Page 109
ATTINY45-20SUR
Manufacturer Part Number
ATTINY45-20SUR
Description
MCU AVR 4KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY45-20SUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATTINY45-20SU SL383
ATTINY45-20SU SL383
ATTINY45-20SU-SL383
Q4272203
ATTINY45-20SU SL383
ATTINY45-20SU-SL383
Q4272203
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14.1
14.1.1
2586M–AVR–07/10
Register Description
DTPS1 – Timer/Counter1 Dead Time Prescaler Register 1
The length of the counting period is user adjustable by selecting the dead time prescaler setting
in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register
consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM
output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can
have different dead time periods. The dead time is adjusted as the number of prescaled dead
time generator clock cycles.
Figure 14-3. The Complementary Output Pair
The dead time prescaler register, DTPS1 is a 2-bit read/write register.
• Bits 1:0 – DTPS1[1:0]: Dead Time Prescaler
The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the
Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can
be generated. The Dead Time prescaler is controlled by two bits DTPS1[1:0] from the Dead
Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The
division factors are given in table 46.
Table 14-1.
Bit
0x23
Read/Write
Initial value
DTPS11
PWM1x
OC1x
OC1x
x = A or B
0
0
1
1
t
non-overlap / rising edge
Division factors of the Dead Time prescaler
R
7
0
DTPS10
0
1
0
1
R
6
0
Prescaler divides the T/C1 clock by
1x (no division)
2x
4x
8x
t
non-overlap / falling edge
R
5
0
R
4
0
R
3
0
R
2
0
DTPS11
R/W
1
0
DTPS10
R/W
0
0
DTPS1
109
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