PIC12LCE518-04/SM Microchip Technology, PIC12LCE518-04/SM Datasheet - Page 32
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12LCE518-04/SM
Manufacturer Part Number
PIC12LCE518-04/SM
Description
IC MCU OTP 512X12 LV W/EE 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Specifications of PIC12LCE518-04/SM
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
768B (512 x 12)
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
25 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
PIC12LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
25 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
For Use With
309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
PIC12C5XX
FIGURE 7-3:
FIGURE 7-4:
7.2
After generating a START condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of opera-
tion is to be performed. The slave address consists of
a 4-bit device code (1010) followed by three don’t care
bits.
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 7-5). The bus is monitored for its cor-
responding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.
DS40139E-page 32
SCL
SDA
SCL
SDA
(A)
Device Addressing
CONDITION
START
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
ACKNOWLEDGE TIMING
1
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
2
3
Data from transmitter
4
ACKNOWLEDGE
ADDRESS OR
VALID
5
(C)
6
TO CHANGE
ALLOWED
7
DATA
Acknowledge
FIGURE 7-5:
8
Start Bit
Bit
S
9
1
Device Select
(D)
1
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
0
Bits
Data from transmitter
CONTROL BYTE FORMAT
Slave Address
1
2
0
1999 Microchip Technology Inc.
3
Read/Write Bit
Don’t Care
X
Acknowledge Bit
Bits
X
X
CONDITION
R/W
STOP
(C)
ACK
(A)