ATTINY24V-10MUR Atmel, ATTINY24V-10MUR Datasheet - Page 33
![MCU AVR 2KB FLASH 10MHZ 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY24V-10MUR
Manufacturer Part Number
ATTINY24V-10MUR
Description
MCU AVR 2KB FLASH 10MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24V-10MUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7. Power Management and Sleep Modes
7.1
7.1.1
8006K–AVR–10/10
Sleep Modes
Idle Mode
The high performance and industry leading code efficiency makes the AVR microcontrollers an
ideal choise for low power applications. In addition, sleep modes enable the application to shut
down unused modules in the MCU, thereby saving power. The AVR provides various sleep
modes allowing the user to tailor the power consumption to the application’s requirements.
Figure 6-1 on page 24
ATtiny24/44/84. The figure is helpful in selecting an appropriate sleep mode.
the different sleep modes and their wake up sources.
Table 7-1.
Note:
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM1:0 bits in the MCUCR Register select which sleep
mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the SLEEP
instruction. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for
some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See
“External Interrupts” on page 49
When the SM1:0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Stand-by
1. For INT0, only level interrupt.
Active Clock Domains and Wake-up Sources in Different Sleep Modes
Table 7-2 on page 37
Active Clock Domains
presents the different clock systems and their distribution in
for details.
X
for a summary.
X
X
Oscillators
X
X
X
X
X
X
(1)
(1)
(1)
ATtiny24/44/84
Wake-up Sources
X
X
CPU
and clk
X
X
Table 7-1
FLASH
X
shows
, while
X
X
X
X
33
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