PIC16HV785-I/SO Microchip Technology, PIC16HV785-I/SO Datasheet - Page 38

• Manufacturer Part Number: PIC16HV785-I/SO
• Description: IC PIC MCU FLASH 2KX14 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16HV785-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC16HV
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• Processor Series: PIC16H
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232, USB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16F785/HV785
REGISTER 4-2:
4.2
Every PORTA pin on the PIC16F785/HV785 has an
interrupt-on-change option and a weak pull-up option.
The next three sections describe these functions.
REGISTER 4-3:
DS41249D-page 36
Additional Pin Functions
bit 7-6
bit 5-0
bit 7-6
bit 5-0
TRISA: PORTA TRI-STATE REGISTER (ADDRESS: 85h, 185h)
WPUA: WEAK PULL-UP REGISTER (ADDRESS: 95h)
bit 7
bit 7
Unimplemented: Read as ‘0’
TRISA<5:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Unimplemented: Read as ‘0’
WPUA<5:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Legend:
R = Readable bit
-n = Value at POR
Legend:
R = Readable bit
-n = Value at POR
Note 1: TRISA<3> always reads ‘1’.
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
U-0
U-0
—
—
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
3: The RA3 pull-up is automatically enabled when configured as MCLR in the
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
(TRISA = 0).
Configuration Word.
U-0
U-0
—
—
TRISA5
WPUA5
R/W-1
R/W-1
Preliminary
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
(2)
(4)
TRISA4
WPUA4
R/W-1
R/W-1
4.2.1
Each of the PORTA pins has an individually config-
urable internal weak pull-up. Control bits WPUAx
enable or disable each pull-up. Refer to Register 4-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the RAPU bit
(OPTION_REG<7>). The weak pull-up on RA3 is auto-
matically enabled when RA3 is configured as MCLR.
(1), (2)
(2)
(4)
WPUA3
TRISA3
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-1
WEAK PULL-UPS
(1)
(3)
TRISA2
WPUA2
R/W-1
R/W-1
(1), (2)
© 2006 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
TRISA1
WPUA1
R/W-1
R/W-1
WPUA0
TRISA0
R/W-1
R/W-1
bit 0
bit 0