ATTINY88-AUR Atmel, ATTINY88-AUR Datasheet - Page 130
ATTINY88-AUR
Manufacturer Part Number
ATTINY88-AUR
Description
MCU AVR 8KB FLASH 12MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY48-MU.pdf
(302 pages)
Specifications of ATTINY88-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.3.1
15.3.2
15.4
15.4.1
130
Data Transfer and Frame Format
ATtiny48/88
TWI Terminology
Electrical Interconnection
Transferring Bits
The following definitions are frequently encountered in this section.
Table 15-1.
The PRTWI bit in
enable the 2-wire Serial Interface.
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line
high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,
and one valid for bus speeds up to 400 kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 15-2. Data Validity
Term
Master
Slave
Transmitter
Receiver
SDA
SCL
TWI Terminology
Figure
Description
The device that initiates and terminates a transmission and generates the SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
“PRR – Power Reduction Register” on page 40
15-1, both bus lines are connected to the positive supply voltage through
Data Stable
“Two-Wire Serial Interface Characteristics” on page
Data Change
Data Stable
must be written to zero to
8008G–AVR–04/11
212. Two
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