ATTINY88-MMH Atmel, ATTINY88-MMH Datasheet - Page 169
![MCU AVR 8KB FLASH 12MHZ 28-VQFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATTINY88-MMH
Manufacturer Part Number
ATTINY88-MMH
Description
MCU AVR 8KB FLASH 12MHZ 28-VQFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY88-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8008G–AVR–04/11
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure
mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. See
Figure 17-7. ADC Timing Diagram, Free Running Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
17-6. This assures a fixed delay from the trigger event to the start of conversion. In this
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
MUX and REFS
Update
1
Conversion
Complete
2
One Conversion
12
3
Sample &
Hold
4
13
Figure
5
14
6
17-7.
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
9
2
MUX and REFS
Update
10
Conversion
Complete
3
11
Sample & Hold
12
4
ATtiny48/88
13
Sign and MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
2
169
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