PIC16C505-04I/P Microchip Technology, PIC16C505-04I/P Datasheet - Page 10
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PIC16C505-04I/P
Manufacturer Part Number
PIC16C505-04I/P
Description
IC MCU OTP 1KX12 14DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16C505-04I/P
Program Memory Type
OTP
Program Memory Size
1.5KB (1K x 12)
Package / Case
14-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
11
Ram Size
72 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
72 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1086 - ADAPTER 14-ZIF BD W/14-SO PLUGS309-1085 - ADAPTER 14-DIP BD W/2 14-SO PLUGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C505-04I/P
Manufacturer:
BOURNS
Quantity:
1 001
Part Number:
PIC16C505-04I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16C505
3.1
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into the instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
FIGURE 3-2:
EXAMPLE 3-1:
DS40192C-page 10
1. MOVLW 03H
2. MOVWF PORTB
3. CALL
4. BSF
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
Clocking Scheme/Instruction Cycle
SUB_1
PORTB, BIT1
OSC1
PC
Q1
Q2
Q3
Q4
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
PC
Q3
Execute 1
Q4
Fetch 2
Q1
Execute INST (PC)
Fetch INST (PC+1)
Execute 2
Q2
Fetch 3
PC+1
3.2
An Instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3 and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
Q1
Fetch SUB_1 Execute SUB_1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
Flush
PC+2
1999 Microchip Technology Inc.
Q3
Q4
Internal
phase
clock