PIC12C672T-04/SM Microchip Technology, PIC12C672T-04/SM Datasheet - Page 487
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PIC12C672T-04/SM
Manufacturer Part Number
PIC12C672T-04/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672T-04/SM
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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Section 26. Watchdog Timer and Sleep Mode
26.2
1997 Microchip Technology Inc.
Control Register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2:0
The OPTION_REG register is a readable and writable register which contains various control bits
to configure the TMR0 prescaler/WDT postscaler, the External INT Interrupt, TMR0, and the
weak pull-ups on PORTB.
Register 26-1: OPTION_REG Register
bit 7
RBPU
1 = Weak pull-ups are disabled
0 = Weak pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS2:PS0: TMR0 Prescaler/WDT Postscaler Rate Select bits
Bit Value
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
RBPU
R/W-1
Note:
Note 1: Some devices call this bit GPPU. Devices that have the RBPU bit, have the weak
000
001
010
011
100
101
110
111
(1)
(1)
: Weak Pull-up Enable bit
To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler
to the Watchdog Timer.
TMR0 Rate
pull-ups on PORTB, while devices that have the GPPU have the weak pull-ups on
the GP Port.
INTEDG
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
R/W-1
WDT Rate
W = Writable bit
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
R/W-1
T0CS
R/W-1
T0SE
- n = Value at POR reset
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
DS31026A-page 26-3
bit 0
R/W-1
PS0
26
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