PIC18F26K20T-I/SS Microchip Technology, PIC18F26K20T-I/SS Datasheet - Page 337
![IC PIC MCU FLASH 32KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18F26K20T-I/SS
Manufacturer Part Number
PIC18F26K20T-I/SS
Description
IC PIC MCU FLASH 32KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
Specifications of PIC18F26K20T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F26K20T-I/SSTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26K20T-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- Current page: 337 of 456
- Download datasheet (4Mb)
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2010 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
CNT
If CNT
PC
If CNT
PC
Q1
Q1
Q1
No
No
No
=
=
=
=
=
register ‘f’
operation
operation
operation
Increment f, skip if 0
INCFSZ
0 f 255
d [0,1]
a [0,1]
(f) + 1 dest,
skip if result = 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
Q2
Q2
No
Q2
No
No
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
by a 2-word instruction.
f {,d {,a}}
INCFSZ
:
:
11da
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
ffff
CNT, 1, 0
destination
operation
operation
operation
Write to
Q4
Q4
Q4
No
No
No
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
PIC18F2XK20/4XK20
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
PC
REG
If REG
PC
If REG
PC
Q1
Q1
No
Q1
=
=
=
=
=
operation
operation
register ‘f’
operation
Increment f, skip if not 0
INFSNZ
0 f 255
d [0,1]
a [0,1]
(f) + 1 dest,
skip if result 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
Q2
Q2
No
Q2
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
3 cycles if skip and followed
by a 2-word instruction.
f {,d {,a}}
INFSNZ
10da
operation
operation
operation
Process
Data
No
No
Q3
Q3
No
Q3
DS41303G-page 337
REG, 1, 0
ffff
destination
operation
operation
operation
Write to
No
No
Q4
Q4
Q4
No
ffff
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