PIC18F26K20T-I/SO Microchip Technology, PIC18F26K20T-I/SO Datasheet - Page 392
![IC PIC MCU FLASH 32KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F26K20T-I/SO
Manufacturer Part Number
PIC18F26K20T-I/SO
Description
IC PIC MCU FLASH 32KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
Specifications of PIC18F26K20T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164303 - MODULE SKT FOR PM3 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18F26K20T-I/SOTR
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- Current page: 392 of 456
- Download datasheet (4Mb)
PIC18F2XK20/4XK20
FIGURE 26-12:
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
DS41303G-page 392
70
71
71A
72
72A
73
73A
74
75
76
78
79
80
Note 1:
Param
No.
(CKP = 0)
(CKP = 1)
SDI
SCK
SDO
SS
SCK
Note:
2:
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
Tb2b
TscH2diL,
TscL2diL
TdoR
TdoF
TscR
TscF
TscH2doV,
TscL2doV
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
Symbol
Refer to Figure 26-4 for load conditions.
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SCK Input High Time
SCK Output Fall Time (Master mode)
SS to SCK or SCK Input
(Slave mode)
SCK Input Low Time
(Slave mode)
Setup Time of SDI Data Input to SCK Edge
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time
(Master mode)
SDO Data Output Valid after SCK Edge
70
80
71
73
MSb In
Characteristic
MSb
74
72
75, 76
Continuous
Single Byte
Continuous
Single Byte
bit 6 - - - - - -1
bit 6 - - - -1
78
79
1.25 T
1.25 T
1.5 T
Min
T
100
100
CY
40
40
—
—
—
—
—
LSb
CY
CY
CY
79
78
LSb In
+ 40
+ 30
+ 30
2010 Microchip Technology Inc.
Max Units
25
25
25
25
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
Conditions
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