PIC16F688-I/ML Microchip Technology, PIC16F688-I/ML Datasheet - Page 296
![IC PIC MCU FLASH 4KX14 16QFN](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F688-I/ML
Manufacturer Part Number
PIC16F688-I/ML
Description
IC PIC MCU FLASH 4KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-IML.pdf
(202 pages)
Specifications of PIC16F688-I/ML
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
16-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART/RS- 232/SCI/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- PIC16F688-IML PDF datasheet #6
- Current page: 296 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.1
DS31017A-page 17-20
Slave Mode
In slave mode, the SCL and SDA pins must be configured as inputs. The SSP module will over-
ride the input state with the output data when required (slave-transmitter).
When an address is matched or the data transfer after an address match is received, the hard-
ware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF reg-
ister with the received value currently in the SSPSR register.
There are certain conditions that will cause the SSP module not to give this ACK pulse. These
are if either (or both):
a)
b)
If the BF bit is set, the SSPSR register value is not loaded into the SSPBUF, but the SSPIF and
SSPOV bits are set.
the status of the BF and SSPOV bits. The shaded cells show the condition where user software
did not properly clear the overflow condition. The BF flag bit is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and low time for proper operation. The high and
low times of the I
parameters 100
The buffer full bit, BF (SSPSTAT<0>), was set before the transfer was received.
The overflow bit, SSPOV (SSPCON1<6>), was set before the transfer was received.
2
and
C specification as well as the requirement of the SSP module is shown in timing
Table 17-2
101
of the
Preliminary
shows what happens when a data transfer byte is received, given
“Electrical Specifications”
section.
1997 Microchip Technology Inc.
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