PIC12C671-10I/SM Microchip Technology, PIC12C671-10I/SM Datasheet - Page 237
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PIC12C671-10I/SM
Manufacturer Part Number
PIC12C671-10I/SM
Description
IC MCU OTP 1KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C671-10I/SM
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
1
Digital
RoHS Compliant
Package
8SOIJ
Device Core
PIC
Family Name
PIC12
Maximum Speed
10 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
5
On-chip Adc
4-chx8-bit
Number Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 237 of 688
- Download datasheet (3Mb)
1997 Microchip Technology Inc.
The SSP module has five registers for I
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I
(SSPCON<3:0>) allow one of the following I
• I
• I
• I
• I
• I
Before selecting any I
the appropriate TRIS bits. Selecting an I
and SDA pins to be used as the clock and data lines in I
The SSPSTAT register gives the status of the data transfer. This information includes detection
of a START or STOP bit, specifies if the received byte was data or address, if the next byte is the
completion of 10-bit address, and if this will be a read or write data transfer.
The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register
shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a
doubled buffered receiver. This allows reception of the next byte to begin before reading the last
byte of received data. When the complete byte is received, it is transferred to the SSPBUF reg-
ister and flag bit SSPIF is set. If another complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and the SSPOV bit (SSPCON<6>) is set and the byte
in the SSPSR is lost.
The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high
byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of
the address needs to be loaded (A7:A0).
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Firmware controlled Multi-Master mode (start and stop bit interrupts enabled)
C Firmware controlled Multi-Master mode (start and stop bit interrupts enabled)
C Firmware controlled Master mode, slave is idle
2
C mode, the SCL and SDA pins must be programmed to inputs by setting
2
C operation. They are:
2
C mode, by setting the SSPEN bit, enables the SCL
2
C modes to be selected:
2
C operation. Four mode selection bits
Section 15. SSP
2
C mode.
DS31015A-page 15-17
15
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