ATTINY25V-15ST Atmel, ATTINY25V-15ST Datasheet - Page 117

• Manufacturer Part Number: ATTINY25V-15ST
• Description: MCU AVR 2K FLASH 4MHZ 8-SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25V-15ST

• Package / Case: 8-SOIC (3.9mm Width)
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 8MHz
• Number Of I /o: 6
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.5
18.5.1
7598H–AVR–07/09
Changing Channel or Reference Selection
ADC Input Channels
Table 18-1.
The MUX3..0 and REFS2..0 bits in the ADMUX Register are single buffered through a tempo-
rary register to which the CPU has random access. This ensures that the channels and voltage
reference selection only takes place at a safe point during the conversion. The channel and volt-
age reference selection is continuously updated until a conversion is started. Once the
conversion starts, the channel and voltage reference selection is locked to ensure a sufficient
sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the
conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following
rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel
or voltage reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the channel
selection. Since the next conversion has already started automatically, the next result will reflect
the previous channel selection. Subsequent conversions will reflect the new channel selection.
Condition
First conversion
Normal conversions
Auto Triggered conversions
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
ADC Conversion Time
Sample & Hold (Cycles from
Start of Conversion)
13.5
1.5
2
ATtiny25/45/85
Total Conversion Time
(Cycles)
13.5
25
13
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