PIC12C672-04I/MF Microchip Technology, PIC12C672-04I/MF Datasheet - Page 266
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PIC12C672-04I/MF
Manufacturer Part Number
PIC12C672-04I/MF
Description
IC MCU OTP 2KX14 A/D 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-04I/MF
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
PIC12C67204I/MF
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PICmicro MID-RANGE MCU FAMILY
DS31016A-page 16-16
The SSP module has five registers for I
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I
(SSPCON<3:0>) allow one of the following I
• I
• I
• I
• I
• I
Before selecting any I
the appropriate TRIS bits. Selecting an I
and SDA pins to be used as the clock and data lines in I
The SSPSTAT register gives the status of the data transfer. This information includes detection
of a START or STOP bit, specifies if the received byte was data or address, if the next byte is the
completion of 10-bit address, and if this will be a read or write data transfer. The SSPSTAT reg-
ister is read only.
The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register
shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a
doubled buffered receiver. This allows reception of the next byte to begin before reading the last
byte of received data. When the complete byte is received, it is transferred to the SSPBUF reg-
ister and the SSPIF flag bit is set. If another complete byte is received before the SSPBUF reg-
ister is read, a receiver overflow has occurred and bit SSPOV (SSPCON<6>) is set.
The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high
byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of
the address needs to be loaded (A7:A0).
enabled)
enabled)
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Firmware controlled Multi-Master mode, 7-bit address (start and stop bit interrupts
C Firmware controlled Multi-Master mode, 10-bit address (start and stop bit interrupts
C Firmware controlled Master mode, slave is idle
2
C mode, the SCL and SDA pins must be programmed to inputs by setting
2
C operation. They are:
2
C mode, by setting the SSPEN bit, enables the SCL
2
C modes to be selected:
2
C operation. Four mode selection bits
2
C mode.
1997 Microchip Technology Inc.
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