PIC16LF818-I/SOTSL Microchip Technology, PIC16LF818-I/SOTSL Datasheet - Page 21
PIC16LF818-I/SOTSL
Manufacturer Part Number
PIC16LF818-I/SOTSL
Description
IC PIC MCU FLASH 1KX14 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(176 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16LF818-I/SOTSL
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16LF818-ISOTSL
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- Current page: 21 of 176
- Download datasheet (4Mb)
2.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4:
2004 Microchip Technology Inc.
Note:
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
PIE1 Register
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
bit 7
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
Unimplemented: Read as ‘0’
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
-n = Value at POR
U-0
—
R/W-0
ADIE
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
SSPIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC16F818/819
CCP1IE
R/W-0
x = Bit is unknown
TMR2IE
R/W-0
DS39598E-page 19
TMR1IE
R/W-0
bit 0
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