PIC16F723-I/ML Microchip Technology, PIC16F723-I/ML Datasheet - Page 30
![IC PIC MCU FLASH 4KX14 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F723-I/ML
Manufacturer Part Number
PIC16F723-I/ML
Description
IC PIC MCU FLASH 4KX14 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.AC164112.pdf
(302 pages)
2.PIC16F722-ISS.pdf
(8 pages)
3.PIC16F722-ISS.pdf
(10 pages)
4.PIC16F722-ISS.pdf
(32 pages)
5.PIC16F722-ISS.pdf
(2 pages)
6.PIC16F722-ISS.pdf
(8 pages)
7.PIC16LF724-IPT.pdf
(266 pages)
Specifications of PIC16F723-I/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
25
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
No. Of Pwm
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- AC164112 PDF datasheet
- PIC16F722-ISS PDF datasheet #2
- PIC16F722-ISS PDF datasheet #3
- PIC16F722-ISS PDF datasheet #4
- PIC16F722-ISS PDF datasheet #5
- PIC16F722-ISS PDF datasheet #6
- PIC16LF724-IPT PDF datasheet #7
- Current page: 30 of 302
- Download datasheet (5Mb)
PIC16F72X/PIC16LF72X
2.3
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from
PCLATH. On any Reset, the PC is cleared. Figure 2-7
shows the two situations for the loading of the PC. The
upper example in Figure 2-7 shows how the PC is
loaded on a write to PCL (PCLATH<4:0> → PCH).
The lower example in Figure 2-7 shows how the PC is
loaded
(PCLATH<4:3> → PCH).
FIGURE 2-7:
2.3.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When perform-
ing a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note AN556, “Implementing a Table Read”
(DS00556).
2.3.2
All devices have an 8-level x 13-bit wide hardware
stack (refer to Figures 2-1 and 2-3). The stack space is
not part of either program or data space and the Stack
Pointer is not readable or writable. The PC is PUSHed
onto the stack when a CALL instruction is executed or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
DS41341E-page 30
PC
PC
12
12 11 10
2
PCL and PCLATH
during
PCH
5
PCLATH<4:3>
PCH
COMPUTED GOTO
STACK
PCLATH
PCLATH<4:0>
8
PCLATH
8
a
7
7
CALL
LOADING OF PC IN
DIFFERENT SITUATIONS
PCL
PCL
or
11
8
GOTO
0
0
OPCODE<10:0>
ALU Result
GOTO, CALL
Instruction with
instruction
Destination
PCL as
2.4
All devices are capable of addressing a continuous 8K
word block of program memory. The CALL and GOTO
instructions provide only 11 bits of address to allow
branching within any 2K program memory page. When
doing a CALL or GOTO instruction, the upper 2 bits of
the address are provided by PCLATH<4:3>. When
doing a CALL or GOTO instruction, the user must ensure
that the page select bits are programmed so that the
desired program memory page is addressed. If a return
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is POPed off the stack. Therefore,
manipulation of the PCLATH<4:3> bits is not required
for the RETURN instructions (which POPs the address
from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
EXAMPLE 2-1:
SUB1_P1
Note:
Note 1: There are no Status bits to indicate stack
2: There are no instructions/mnemonics
Program Memory Paging
ORG 500h
PAGESEL SUB_P1 ;Select page 1
CALL
:
:
ORG
:
:
RETURN
The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis-
ter for any subsequent subroutine calls or
GOTO instructions.
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN,
tions or the vectoring to an interrupt
address.
SUB1_P1 ;Call subroutine in
900h
IN PAGE 1 FROM PAGE 0
CALL OF A SUBROUTINE
RETLW and RETFIE instruc-
© 2009 Microchip Technology Inc.
;(800h-FFFh)
;page 1 (800h-FFFh)
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to
;Call subroutine
;in page 0
;(000h-7FFh)
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