ATMEGA88-20AUR Atmel, ATMEGA88-20AUR Datasheet - Page 79

• Manufacturer Part Number: ATMEGA88-20AUR
• Description: MCU AVR 8K FLASH 20MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88-20AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2545S–AVR–07/10
OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the
Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set
(one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer
function.
PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.
• ICP1/CLKO/PCINT0 – Port B, Bit 0
ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.
CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTB0 and DDB0 settings. It will also be output during reset.
PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.
Table 13-4
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 13-4.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 13-5 on page
and
PB7/XTAL2/
TOSC2/PCINT7
INTRC • EXTCK+
AS2
0
INTRC • EXTCK+
AS2
0
0
0
INTRC • EXTCK +
AS2 + PCINT7 •
PCIE0
(INTRC + EXTCK) •
AS2
PCINT7 INPUT
Oscillator Output
Overriding Signals for Alternate Functions in PB7..PB4
Table 13-5
(1)
relate the alternate functions of Port B to the overriding signals
75. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/XTAL1/
TOSC1/PCINT6
INTRC + AS2
0
INTRC + AS2
0
0
0
INTRC + AS2 +
PCINT6 • PCIE0
INTRC • AS2
PCINT6 INPUT
Oscillator/Clock
Input
(1)
PB5/SCK/
PCINT5
SPE • MSTR
PORTB5 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
PCINT5 • PCIE0
1
PCINT5 INPUT
SCK INPUT
–
ATmega48/88/168
PB4/MISO/
PCINT4
SPE • MSTR
PORTB4 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE
OUTPUT
PCINT4 • PCIE0
1
PCINT4 INPUT
SPI MSTR INPUT
–
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