PIC16C716-04E/SO Microchip Technology, PIC16C716-04E/SO Datasheet - Page 67

• Manufacturer Part Number: PIC16C716-04E/SO
• Description: IC MCU OTP 2KX14 A/D PWM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C716-04E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
9.13.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
FIGURE 9-17:
9.14
If
programmed, the on-chip program memory can be
read out for verification purposes.
© 2005 Microchip Technology Inc.
Note 1:
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
Note:
INSTRUCTION FLOW
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
the
Instruction
fetched
Instruction
executed
CLKOUT(4)
2:
3:
4:
INT pin
OSC1
Program Verification/Code
Protection
code
PC
XT, HS or LP Oscillator mode assumed.
T
GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
OST
WAKE-UP USING INTERRUPTS
Microchip does not recommend code
protecting windowed devices.
Inst(PC) = Sleep
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
protection
PC
OSC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
(drawing not to scale) This delay will not be there for RC Osc mode.
Q1 Q2 Q3 Q4
bit(s)
Inst(PC + 1)
Sleep
PC + 1
have
Q1
Processor in
not
Sleep
PC + 2
been
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
9.15
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during Program/Verify. It is
recommended that only the 4 Least Significant bits of
the ID location are used.
For ROM devices, these values are submitted along
with the ROM code.
PC + 2
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
tion of a SLEEP instruction, the device will imme-
diately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
ID Locations
Interrupt Latency
Dummy cycle
(Note 2)
PC + 2
PIC16C712/716
Q1 Q2 Q3 Q4
Inst(0004h)
Dummy cycle
0004h
DS41106B-page 65
Q1 Q2 Q3 Q4
Inst(0005h)
Inst(0004h)
0005h