PIC16F819T-E/SS Microchip Technology, PIC16F819T-E/SS Datasheet - Page 116
![IC PIC MCU FLASH 2KX14 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F819T-E/SS
Manufacturer Part Number
PIC16F819T-E/SS
Description
IC PIC MCU FLASH 2KX14 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F819T-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F819T-E/SS
Manufacturer:
SHOEI
Quantity:
60 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 116 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
7.3
7.4
DS31007A-page 7-4
EEADR
EECON1 and EECON2 Registers
The EEADR register can address up to a maximum of 256 bytes of data EEPROM.
The unused address bits are decoded. This means that these bits must always be '0' to ensure
that the address is in the Data EEPROM memory space.
EECON1 is the control register with five low order bits physically implemented. The upper-three
bits are unimplemented and read as '0's.
Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at completion of the read or write operation. The
inability to clear the WR bit in software prevents the accidental, premature termination of a write
operation.
The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time-out reset
during normal operation. In these situations, following reset, the user can check the WRERR bit
and rewrite the location. The data and address will be unchanged in the EEDATA and
EEADR registers.
Interrupt flag bit EEIF is set when write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is
used exclusively in the Data EEPROM write sequence.
1997 Microchip Technology Inc.
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