PIC18LF13K22-I/ML Microchip Technology, PIC18LF13K22-I/ML Datasheet - Page 26

• Manufacturer Part Number: PIC18LF13K22-I/ML
• Description: IC PIC MCU FLASH 256KX8 20-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, MSSP, SPI, USART
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
6.0
The PIC18F1XK22/LF1XK22 devices have several
Configuration Words. These bits can be set or cleared
to select various device configurations. All other mem-
ory areas should be programmed and verified prior to
setting Configuration Words. These bits may be read
out normally, even after read or code protection. See
Table 6-1 for a list of Configuration bits and device IDs
and Table 6-3 for the Configuration bit descriptions.
6.1
A user may store identification information (ID) in eight
ID locations mapped in 200000h:200007h. It is recom-
mended that the Most Significant nibble of each ID be
Fh. In doing so, if the user code inadvertently tries to
execute from the ID space, the ID data will execute as
a NOP.
TABLE 6-1:
DS41357B-page 26
300001h
300002h
300003h
300005h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFEh
3FFFFFh
Legend:
Note
File Name
1:
2:
CONFIGURATION WORD
ID Locations
DEVID1
DEVID2
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3H
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
x = unknown, u = unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.
These bits are only implemented on specific devices. Refer to Section 3.0 “Memory Maps” to determine which bits apply based on
available memory.
DEVID registers are read-only and cannot be programmed by the user.
(2)
(2)
CONFIGURATION BITS AND DEVICE IDs
MCLRE
BKBUG
DEV10
WRTD
DEV2
IESO
Bit 7
CPD
—
—
—
—
—
—
ENHCPU
FCMEN
EBTRB
WRTB
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
—
PRI_CLK_EN
WRTC
DEV0
DEV8
Bit 5
—
—
—
—
—
—
—
—
—
Advance Information
PLL_EN
WDPS3
BORV1
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
6.2
The device ID word for the PIC18F1XK22/LF1XK22
devices is located at 3FFFFEh:3FFFFFh. These bits
may be used by the programmer to identify what device
type is being programmed and read out normally, even
after code or read protection. See Table 6-2 for a
complete list of device ID values.
FIGURE 6-1:
HFOFST
WDPS2
FOSC3
BORV0
BBSIZ
REV3
DEV6
Bit 3
—
—
—
—
—
—
Device ID Word
BOREN1
WDPS1
FOSC2
DEV5
REV2
Bit 2
LVP
—
—
—
—
—
—
—
Set TBLPTR = 3FFFFE
with Post-Increment
with Post-Increment
Read High Byte
Read Low Byte
BOREN0
WDPS0
FOSC1
EBTR1
WRT1
READ DEVICE ID WORD
FLOW
REV1
DEV4
Bit 1
CP1
© 2009 Microchip Technology Inc.
—
—
—
—
—
Done
Start
PWRTEN
STVREN
WDTEN
FOSC0
EBTR0
WRT0
REV0
DEV3
Bit 0
CP0
—
—
—
—
Unprogrammed
See Table 6-2
See Table 6-2
0010 0111
---1 1111
---1 1111
1--- 1---
10-- 01-1
---- --11
11-- ----
---- --11
111- ----
---- --11
-1-- ----
Default/
Value