PIC16F819-I/SSTSL Microchip Technology, PIC16F819-I/SSTSL Datasheet - Page 93
![IC PIC MCU FLASH 2KX14 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F819-I/SSTSL
Manufacturer Part Number
PIC16F819-I/SSTSL
Description
IC PIC MCU FLASH 2KX14 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F819-I/SSTSL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 93 of 176
- Download datasheet (4Mb)
12.2
The PIC16F818/819 differentiates between various
kinds of Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT Reset during normal operation
• WDT wake-up during Sleep
• Brown-out Reset (BOR)
FIGURE 12-1:
2004 Microchip Technology Inc.
MCLR
OSC1
V
DD
Reset
31.25 kHz
INTRC
OST/PWRT
Brown-out
V
Module
Detect
DD
WDT
Reset
Rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
PWRT
10-bit Ripple Counter
Time-out
Reset
WDT
10-bit Ripple Counter
BOREN
Power-on Reset
External
Reset
Sleep
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations as indicated in
Table 12-3. These bits are used in software to
determine the nature of the Reset. Upon a POR, BOR
or
approximately 5-10 s to become ready for code
execution. This delay runs in parallel with any other
timers. See Table 12-4 for a full description of Reset
states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 12-1.
wake-up
PIC16F818/819
from
Sleep,
S
R
the
Q
DS39598E-page 91
CPU
Chip_Reset
Enable PWRT
Enable OST
requires
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