PIC16LC770-I/SS Microchip Technology, PIC16LC770-I/SS Datasheet - Page 123
![IC MCU OTP 2KX14 A/D PWM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16LC770-I/SS
Manufacturer Part Number
PIC16LC770-I/SS
Description
IC MCU OTP 2KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC770-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LC770I/SS
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12.3
The PIC16C717/770/771 devices have several differ-
ent RESETS. These RESETS are grouped into two
classifications; power-up and non-power-up. The
power-up type RESETS are the Power-on and Brown-
out Resets which assume the device V
normal operating range for the device’s configuration.
The non power-up type RESETS assume normal oper-
ating limits were maintained before/during and after the
RESET.
• Power-on Reset (POR)
• Programmable Brown-out Reset (PBOR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (during normal operation)
FIGURE 12-4:
2002 Microchip Technology Inc.
MCLR
OSC1
V
DD
RESET
Dedicated
Oscillator
OST/PWRT
Programmable
V
Module
Brown-out
detect
WDT
DD
rise
OST
PWRT
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Time-out
10-bit Ripple counter
Power-on Reset
10-bit Ripple counter
BODEN
External
RESET
SLEEP
DD
was below its
Enable PWRT
Enable OST
Some registers are not affected in any RESET condi-
tion. Their status is unknown on a Power-up Reset and
unchanged in any other RESET. Most other registers
are placed into an initialized state upon RESET, how-
ever they are not affected by a WDT Reset during
SLEEP, because this is considered a WDT Wake-up,
which is viewed as the resumption of normal operation.
Several status bits have been provided to indicate
which RESET occurred (see
Table 12-6 for a full description of RESET states of all
registers.
A simplified block diagram of the On-Chip Reset circuit
is shown in Figure 12-4.
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
PIC16C717/770/771
S
R
DS41120B-page 121
Table 12-4).
Q
Chip_Reset
See
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