PIC16C554-20/SO Microchip Technology, PIC16C554-20/SO Datasheet - Page 23

• Manufacturer Part Number: PIC16C554-20/SO
• Description: IC MCU OTP 512X14 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C554-20/SO

• Core Size: 8-Bit
• Program Memory Size: 896B (512 x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: OTP
• Ram Size: 80 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 13
• Ram Memory Size: 80Byte
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 80 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

4.3
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high bits (PC<12:8>) are not
directly readable or writable and come from PCLATH.
On any RESET, the PC is cleared. Figure 4-6 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH). The lower exam-
ple in Figure 4-6 shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-6:
4.3.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
4.3.2
The PIC16C55X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-1 and Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not affected by a
PUSH or POP operation.
 2002 Microchip Technology Inc.
PC
PC
12
12
2
11 10
PCL and PCLATH
5
PCH
PCLATH<4:3>
PCH
COMPUTED GOTO
STACK
PCLATH
PCLATH<4:0>
8
PCLATH
8
7
7
LOADING OF PC IN
DIFFERENT SITUATIONS
PCL
PCL
11
8
0
0
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
Preliminary
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
4.4
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no-
operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-7. However, IRP is not used in the
PIC16C55X.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1:
NEXT
CONTINUE:
Note 1: There are no status bits to indicate stack
Indirect Addressing, INDF and
FSR Registers
2: There are no instructions mnemonics
movlw
movwf
clrf
incf
btfss
goto
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or vectoring to an interrupt
address.
0x20
FSR
INDF
FSR
FSR,4 ;all done?
NEXT
INDIRECT ADDRESSING
PIC16C55X
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;no clear next
;yes continue
DS40143D-page 21