PIC16C716-20E/SS Microchip Technology, PIC16C716-20E/SS Datasheet - Page 27
![IC MCU OTP 2KX14 A/D PWM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16C716-20E/SS
Manufacturer Part Number
PIC16C716-20E/SS
Description
IC MCU OTP 2KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16C716-20E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
For Use With
309-1016 - ADAPTER 20-SSOP TO 18-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
PORTB pins RB3:RB1 are multiplexed with several
peripheral functions (Table 3-3). PORTB pins RB3:RB0
have Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISB as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins, RB7:RB4, are
compared with the old value latched on the last read of
FIGURE 3-4:
© 2005 Microchip Technology Inc.
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
Data Bus
RD
DATACCP
WR
DATACCP
WR
TRISCCP
WR
PORTB
WR TRISB
T1OSCEN
TMR1CS
BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
TMR1CS
RD PORTB
TRISCCP<0>
DATACCP<0>
PORTB<1>
TRISB<1>
D
D
D
D
CK
CK
CK
CK
Q
Q
Q
Q
Q
Q
Q
Q
1
0
RBPU
T1OSCEN
T1CS
(1)
T1CLKIN
1
0
TTL Buffer
1
1
0
0
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Any read or write of PORTB will end the
mismatch condition.
Clear flag bit RBIF.
ST
Buffer
V
P
DD
Weak
Pull-up
PIC16C712/716
V
SS
V
DD
RB1/T1OSO/T1CKI
DS41106B-page 25