PIC16C771-I/SS Microchip Technology, PIC16C771-I/SS Datasheet - Page 138
![IC MCU OTP 4KX14 A/D PWM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16C771-I/SS
Manufacturer Part Number
PIC16C771-I/SS
Description
IC MCU OTP 4KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C770-ISO.pdf
(220 pages)
2.PIC16C770-ISO.pdf
(6 pages)
3.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C771-I/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
15
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Controller Family/series
PIC16C
No. Of I/o's
16
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP309-1014 - ADAPTER 20-SSOP TO 20-DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16C771I/SS
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PIC16C717/770/771
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41120B-page 136
Bit Test, Skip if Clear
[label] BTFSC f,b
0
0
skip if (f<b>) = 0
None
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2T
Bit Test f, Skip if Set
[label] BTFSS f,b
0
0
skip if (f<b>) = 1
None
If bit ’b’ in register ’f’ is ’0’, the next
instruction is executed.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOP is exe-
cuted instead making this a 2T
instruction.
Call Subroutine
[ label ] CALL k
0
(PC)+ 1
k
(PCLATH<4:3>)
None
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two cycle instruction.
f
b < 7
f
b
k
PC<10:0>,
127
127
7
2047
CY
TOS,
instruction.
PC<12:11>
CY
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
Clear W
[ label ] CLRW
None
00h
1
Z
W register is cleared. Zero bit (Z)
is set.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h
0
1
1
TO, PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
Clear f
[label] CLRF
0
00h
1
Z
The contents of register ’f’ are
cleared and the Z bit is set.
f
Z
WDT prescaler,
TO
PD
Z
2002 Microchip Technology Inc.
127
(W)
WDT
(f)
f
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