PIC12C671-10/SM Microchip Technology, PIC12C671-10/SM Datasheet - Page 162
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PIC12C671-10/SM
Manufacturer Part Number
PIC12C671-10/SM
Description
IC MCU OTP 1KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C671-10/SM
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
PIC12C671-10/SMR
PIC12C671-10/SMR
PIC12C671-10/SMR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12C671-10/SM
Manufacturer:
Microchip Technology
Quantity:
135
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PICmicro MID-RANGE MCU FAMILY
10.1
DS31010A-page 10-2
Introduction
Some devices have an 8-bit wide Parallel Slave Port (PSP). This port is multiplexed onto one of
the devices I/O ports. The PORT operates as an 8-bit wide Parallel Slave Port, or microprocessor
port, when the PSPMODE control bit is set. In this mode, the input buffers are TTL.
In slave mode the module is asynchronously readable and writable by the external world through
RD control input pin and the WR control input pin.
It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORT latch as an 8-bit latch. Setting the PSPMODE bit enables port pins to be
the RD input, the WR input, and the CS (chip select) input.
There are actually two 8-bit latches, one for data-out (from the PICmicro) and one for data input.
The user writes 8-bit data to PORT data latch and reads data from the port pin latch (note that
they have the same address). In this mode, the TRIS register is ignored, since the microproces-
sor is controlling the direction of data flow.
Figure 10-1
Figure 10-1: PORTD and PORTE Block Diagram (Parallel Slave Port)
Note 1: At present the Parallel Slave Port (PSP) is only multiplexed onto PORTD and
Note 2: In this mode the PORTD and PORTE input buffers are TTL. The control bits for the
Note: I/O pins have protection diodes to V
Data bus
One bit of PORTD
Set interrupt flag
PSPIF
PORTE. The microprocessor port becomes enabled when the PSPMODE bit is set.
In this mode, the user must make sure that PORTD and PORTE are configured as
digital I/O. That is, peripheral modules multiplexed onto the PSP functions are dis-
abled (such as the A/D).
When PORTE is configured for digital I/O. PORTD will override the values in the
TRISD register.
PSP operation are located in TRISE.
shows the block diagram for the PSP.
RD Port
WR Port
Q
D
CK
EN
EN
EN
D
Q
DD
and V
SS
.
TTL
Read
Chip Select
Write
1997 Microchip Technology Inc.
TTL
TTL
TTL
PSP7:PSP0
RD
CS
WR
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