PIC16LC771-I/SS Microchip Technology, PIC16LC771-I/SS Datasheet - Page 80

• Manufacturer Part Number: PIC16LC771-I/SS
• Description: IC MCU OTP 4KX14 A/D PWM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC771-I/SS

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC16LC
• No. Of I/o's: 15
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• Core: PIC
• Processor Series: PIC16LC
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 256 B
• Data Rom Size: 256 B
• On-chip Adc: 6
• Number Of Programmable I/os: 16
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: SMD/SMT
• Height: 1.75 mm
• Interface Type: I2C, SPI, SSP
• Length: 7.2 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Width: 5.3 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16LC771I/SS

PIC16C717/770/771
9.2.2.3
When the R/W bit of the address byte is clear
(SSPSR<0> = 0) and an address match occurs, the R/
W bit of the SSPSTAT register is cleared. The received
address is loaded into the SSPBUF register on the fall-
ing edge of the eighth SCL pulse.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) or
bit SSPOV (SSPCON<6>) is set.
TABLE 9-2:
FIGURE 9-8:
DS41120B-page 78
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Transfer is Received
Status Bits as Data
BF
0
1
1
0
S
SLAVE RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
SSPOV
2
Receiving Address
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
3
I
2
4
C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
5
6
SSPSR
7
R/W=0
8
ACK
9
Yes
Yes
No
No
Advance Information
D7
SSPBUF
1
D6
2
SSPBUF register is read
Cleared in software
Receiving Data
D5
3
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
Generate ACK
D1
7
Note:
Pulse
D0
8
Yes
No
No
No
ACK
9
NACK is sent because of overflow
The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSP-
BUF is updated.
D7
1
D6
2
D5
Receiving Data
3
D4
4
(SSP Interrupt occurs
D3
2002 Microchip Technology Inc.
5
D2
6
Set bit SSPIF
if enabled)
D1
7
Yes
Yes
Yes
Yes
D0
8
NACK
9
Bus Master
transfer
terminates
P