PIC16C433-E/SO Microchip Technology, PIC16C433-E/SO Datasheet - Page 27

• Manufacturer Part Number: PIC16C433-E/SO
• Description: IC MCU CMOS 8BIT 10MHZ 2K 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C433-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-SOIC (7.5mm Width)
• For Use With: AC164030 - MODULE SKT PROMATEII 28DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.0
As with any other register, the I/O register can be writ-
ten and read under program control. However, read
instructions (i.e., MOVF GPIO,W) always read the I/O
pins independent of the pin’s Input/Output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance), since the I/O control registers are all
set.
5.1
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP<5:0>). Bits 6 and 7 (LINTX and LINRX,
respectively) are used by the LIN bus transceiver
peripheral. Please note that GP3 is an input only pin.
The configuration word can set several I/O’s to alter-
nate functions. When acting as alternate functions, the
pins will read as ‘0’ during port read. Pins GP0, GP1
and GP3 can be configured with weak pull-ups and
also with interrupt-on-change. The interrupt-on-change
and weak pull-up functions are not pin selectable. If pin
4 (GP3), is configured as MCLR, a weak pull-up is
always on. Interrupt-on-change for this pin is not set
and GP3 will read as '0'. Interrupt-on-change is
enabled by setting bit GPIE, INTCON<3>. Note that
external oscillator use overrides the GPIO functions on
GP4 and GP5.
5.2
This register controls the data direction for GPIO. A '1'
from a TRIS Register bit puts the corresponding output
driver in a Hi-impedance mode. A '0' puts the contents
of the output data latch on the selected pins, enabling
the output buffer. The exceptions are GP3, which is
input only and its TRIS bit will always read as '1', while
GP6 and GP7 TRIS bits will read as ’0’.
Upon RESET, the TRIS Register is all '1's, making all
pins inputs.
TRIS for pins GP4 and GP5 is forced to a ’1’, where
appropriate. Writes to TRIS <5:4> will have an effect in
EXTRC and INTRC oscillator modes only. When GP4
is configured as CLKOUT, changes to TRIS<4> will
have no effect.
5.3
The equivalent circuit for an I/O port pin is shown in
Figure 5-1 through Figure 5-5. All port pins, except
GP3, which is input only, may be used for both input
and output operations. For input operations, these
ports are non-latching. Any input must be present until
read by an input instruction (i.e., MOVF GPIO,W). The
 2002 Microchip Technology Inc.
Note:
I/O PORT
GPIO
TRIS Register
I/O Interfacing
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Preliminary
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output, the
corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
Port pins LINTX and LINRX are used for the LIN bus
transceiver. These port pins are not available externally
on the package. Users should avoid writing to pins GP6
(SDA) and GP7 (SCL), when not communicating with
the LIN bus transceiver.
Note:
On a Power-on Reset, GP0, GP1, GP2
and GP4 are configured as analog inputs
and read as '0'.
PIC16C433
DS41139B-page 25