PIC18F45K20-I/ML Microchip Technology, PIC18F45K20-I/ML Datasheet - Page 23

• Manufacturer Part Number: PIC18F45K20-I/ML
• Description: IC PIC MCU FLASH 16KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.5
The code sequence detailed in Table 3-5 should be
used, except that the address used in “Step 2” will be in
the range of 000000h to 0007FFh.
TABLE 3-9:
FIGURE 3-8:
© 2009 Microchip Technology Inc.
Step 1: Direct access to config memory.
0000
0000
0000
Step 2
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
1111
0000
Note 1:
Command
4-bit
(1)
Boot Block Programming
: Set Table Pointer for config byte to be written. Write even/odd addresses.
Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of
Configuration bits. Always write all the Configuration bits before enabling the write protection for
Configuration bits.
<MSB ignored><LSB>
<MSB><LSB ignored>
SET ADDRESS POINTER TO CONFIGURATION LOCATION
Data Payload
CONFIGURATION PROGRAMMING FLOW
Delay P9 and P10
Time for Write
8E A6
8C A6
6E F8
6E F7
6E F6
6E F6
Configuration
84 A6
0E 30
0E 00
0E 00
0E 01
00 00
00 00
Load Even
Program
Address
Done
Start
LSB
BSF EECON1, EEPGD
BSF EECON1, CFGS
BSF EECON1, WREN
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
MOVLW 01h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9A and low for time P10.
Advance Information
3.6
Unlike code memory, the Configuration bits are
programmed a byte at a time. The Table Write, Begin
Programming 4-bit command (‘1111’) is used, but only
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses
and the MSB will be written to odd addresses. The
code sequence to program two consecutive configura-
tion locations is shown in Table 3-9. See Figure 3-5 for
the timing diagram.
PIC18F2XK20/4XK20
Note:
Core Instruction
Configuration Bits Programming
Delay P9 and P10
The address must be explicitly written for
each byte programmed. The addresses
can not be incremented in this mode.
Time for Write
Configuration
Load Odd
Program
Address
Start
MSB
Done
DS41297F-page 23