PIC16F870T-I/SS Microchip Technology, PIC16F870T-I/SS Datasheet - Page 293
![IC MCU FLASH 2KX14 EE 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16F870T-I/SS
Manufacturer Part Number
PIC16F870T-I/SS
Description
IC MCU FLASH 2KX14 EE 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F870-ISO.pdf
(172 pages)
4.PIC16F870-ISO.pdf
(6 pages)
Specifications of PIC16F870T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
For Use With
I3-DB16F871 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F870-ISO PDF datasheet #3
- PIC16F870-ISO PDF datasheet #4
- Current page: 293 of 688
- Download datasheet (3Mb)
17.3.7
17.3.8
INTCON
PIR
PIE
SSPBUF
SSPCON1
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Note 1: The position of this bit is device dependent.
1997 Microchip Technology Inc.
Name
2: These bits may also be named GPIE and GPIF.
Shaded cells are not used by the SSP in SPI mode.
Sleep Operation
Effects of a Reset
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
Bit 7
SMP
GIE
In master mode all module clocks are halted, and the transmission/reception will remain in that
state until the device wakes from sleep. After the device returns to normal mode, the module will
continue to transmit/receive data.
In slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This
allows the device to be placed in sleep mode, and data to be shifted into the SPI transmit/receive
shift register. When all 8-bits have been received, the MSSP interrupt flag bit will be set and if
enabled will wake the device from sleep.
A reset disables the MSSP module and terminates the current transfer.
Table 17-1: Registers Associated with SPI Operation
PEIE
Bit 6
CKE
Bit 5
T0IE
D/A
INTE RBIE
Bit 4
P
SSPIF
SSPIE
Preliminary
Bit 3
S
(1)
(1)
(2)
Bit 2
T0IF
R/W
INTF
Bit 1
Section 17. MSSP
UA
RBIF
Bit 0
BF
(2)
0000 0000
xxxx xxxx
0000 0000
0000 0000
Value on
POR,
BOR
0
0
DS31017A-page 17-17
other resets
Value on all
0000 0000
uuuu uuuu
0000 0000
0000 0000
0
0
17
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