PIC16C554-04I/SS Microchip Technology, PIC16C554-04I/SS Datasheet - Page 47

• Manufacturer Part Number: PIC16C554-04I/SS
• Description: IC MCU OTP 512X14 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C554-04I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 896B (512 x 14)
• Program Memory Type: OTP
• Ram Size: 80 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 80 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• For Use With: 309-1016 - ADAPTER 20-SSOP TO 18-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

6.8
The Power-down mode is entered by executing a
SLEEP
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before
impedance).
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
V
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
6.8.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
FIGURE 6-14:
 2002 Microchip Technology Inc.
SS
Note
Note:
(INTCON<1>)
(INTCON<7>)
INSTRUCTION FLOW
External RESET input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin or RB Port change
for lowest current consumption. The contribution
CLKOUT
Instruction
Instruction
INTF flag
executed
SLEEP
instruction.
INT pin
fetched
GIE bit
1:
2:
3:
4:
Power-Down Mode (SLEEP)
OSC1
It should be noted that a RESET generated
by a WDT timeout does not drive MCLR
pin low.
PC
WAKE-UP FROM SLEEP
XT, HS or LP Oscillator mode assumed.
T
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
(4)
OST
was executed (driving high, low, or hi-
Inst(PC) = SLEEP
= 1024T
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC - 1)
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
DD
(drawing not to scale). This delay will not be there for RC osc mode.
, or V
Inst(PC + 1)
SLEEP
PC+1
SS
, with no external
Processor in
IHMC
SLEEP
DD
).
Preliminary
PC+2
or
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
The first event will cause a device RESET. The two lat-
ter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
set (enabled), the device executes the instruction after
the
rupt address (0004h). In cases where the execution of
the instruction following
user should have an
The WDT is cleared when the device wakes-up from
SLEEP, regardless of the source of wake-up.
Inst(PC + 2)
Inst(PC + 1)
Note:
PC+2
SLEEP
SLEEP
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
instruction and then branches to the inter-
Interrupt Latency
Dummy cycle
PC + 2
instruction is being executed, the
SLEEP
NOP
SLEEP
PIC16C55X
(2)
after the
instruction. If the GIE bit is
Inst(0004h)
Dummy cycle
0004h
is not desirable, the
SLEEP
DS40143D-page 45
Inst(0005h)
Inst(0004h)
instruction.
0005h