PIC16C620-04/SO Microchip Technology, PIC16C620-04/SO Datasheet - Page 60

• Manufacturer Part Number: PIC16C620-04/SO
• Description: IC MCU OTP 512X14 COMP 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C620-04/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 896B (512 x 14)
• Program Memory Type: OTP
• Ram Size: 80 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PIC16C62X
9.7
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the
configuration bit WDTE as clear (Section 9.1).
9.7.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
FIGURE 9-17:
TABLE 9-7:
DS30235J-page 58
Address Name
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note:
Note:
DD
instruction. During normal operation, a WDT
Watchdog Timer (WDT)
and process variations from part to part (see
Config. bits —
OPTION
WDT PERIOD
_
+ = Reserved for future use
= Unimplemented location, read as “0”
T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
SUMMARY OF WATCHDOG TIMER REGISTERS
RBPU
WATCHDOG TIMER BLOCK DIAGRAM
Bit 7
Enable Bit
Watchdog
BODEN
INTEDG
Timer
WDT
Bit 6
From TMR0 Clock Source
CP1
T0CS
Bit 5
(Figure 6-6)
CP0
T0SE
1
Bit 4
0
PSA
M
U
X
PWRTE
PSA
Bit 3
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
It should also be taken in account that under worst case
conditions (V
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
WDTE
PS2
Bit 2
CLRWDT
0
Time-out
MUX
8 - to -1 MUX
WDT
Postscaler
FOSC1
WDT PROGRAMMING
CONSIDERATIONS
PS1
DD
Bit 1
and
1
= Min., Temperature = Max., max.
8
SLEEP
FOSC0
PS0
Bit 0
 2003 Microchip Technology Inc.
To TMR0 (Figure 6-6)
PSA
instructions clear the WDT
—
1111 1111
POR Reset
PS<2:0>
Value on
—
1111 1111
Value on all
RESETS
other