PIC16F72-I/SS Microchip Technology, PIC16F72-I/SS Datasheet - Page 116

• Manufacturer Part Number: PIC16F72-I/SS
• Description: IC PIC MCU FLASH 2KX14 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 8-bit
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
7.3
7.4
DS31007A-page 7-4
EEADR
EECON1 and EECON2 Registers
The EEADR register can address up to a maximum of 256 bytes of data EEPROM.
The unused address bits are decoded. This means that these bits must always be '0' to ensure
that the address is in the Data EEPROM memory space.
EECON1 is the control register with five low order bits physically implemented. The upper-three
bits are unimplemented and read as '0's.
Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at completion of the read or write operation. The
inability to clear the WR bit in software prevents the accidental, premature termination of a write
operation.
The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time-out reset
during normal operation. In these situations, following reset, the user can check the WRERR bit
and rewrite the location. The data and address will be unchanged in the EEDATA and
EEADR registers.
Interrupt flag bit EEIF is set when write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is
used exclusively in the Data EEPROM write sequence.
1997 Microchip Technology Inc.