PIC18F24J11-I/ML Microchip Technology, PIC18F24J11-I/ML Datasheet - Page 336
![IC PIC MCU FLASH 16K 2V 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F24J11-I/ML
Manufacturer Part Number
PIC18F24J11-I/ML
Description
IC PIC MCU FLASH 16K 2V 28-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F24J11-I/ML
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
16
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Embedded Interface Type
EUSART, I2C, SPI
Rohs Compliant
Yes
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F24J11-I/ML
Manufacturer:
MICROCHIP
Quantity:
49 000
- Current page: 336 of 528
- Download datasheet (8Mb)
PIC18F46J11 FAMILY
19.2.5
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The Frame Break character is sent whenever
the SENDB and TXEN bits (TXSTAx<3> and
TXSTAx<5>) are set while the Transmit Shift Register
is loaded with data.
Note that the value of data written to TXREGx will be
ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREGx for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 19-10 for the timing of the Break
character sequence.
FIGURE 19-10:
DS39932C-page 336
Reg. Empty Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREGx
(Transmit Buffer
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
SENDB bit
TRMT bit
TXx (pin)
TXxIF bit
BREAK CHARACTER SEQUENCE
SEND BREAK CHARACTER SEQUENCE
Dummy Write
SENDB sampled here
Start Bit
Bit 0
Bit 1
Break
19.2.5.1
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus master.
1.
2.
3.
4.
5.
When the TXREGx becomes empty, as indicated by the
TXxIF, the next data byte can be written to TXREGx.
19.2.6
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the auto-wake-up feature
described in Section 19.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on
RXx/DTx, cause an RCxIF interrupt and receive the
next data byte followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABDEN
bit once the TXxIF interrupt is observed.
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to set up the
Break character.
Load the TXREGx with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREGx to load the Sync
character into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
RECEIVING A BREAK CHARACTER
Break and Sync Transmit Sequence
Bit 11
Auto-Cleared
© 2009 Microchip Technology Inc.
Stop Bit
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