PIC18F87J11T-I/PT Microchip Technology, PIC18F87J11T-I/PT Datasheet - Page 100
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PIC18F87J11T-I/PT
Manufacturer Part Number
PIC18F87J11T-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(448 pages)
3.PIC18F63J11-IPT.pdf
(36 pages)
4.PIC18F66J11-IPT.pdf
(20 pages)
5.PIC18F84J11-IPT.pdf
(24 pages)
Specifications of PIC18F87J11T-I/PT
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
48MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Type
FLASH
Ram Size
3930 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
68
Ram Memory Size
3930Byte
Cpu Speed
48MHz
No. Of Timers
5
No. Of Pwm
RoHS Compliant
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 15 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164136 - DEVELOPMENT KIT FOR PIC18AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F87J11T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- PIC18F63J11-IPT PDF datasheet #3
- PIC18F66J11-IPT PDF datasheet #4
- PIC18F84J11-IPT PDF datasheet #5
- Current page: 100 of 448
- Download datasheet (8Mb)
PIC18F87J11 FAMILY
7.1
The operation of the interface is controlled by the
MEMCON register (Register 7-1). This register is
available in all program memory operating modes
except Microcontroller mode. In this mode, the register
is disabled and cannot be written to.
The EBDIS bit (MEMCON<7>) controls the operation
of the bus and related port functions. Clearing EBDIS
enables the interface and disables the I/O functions of
the ports, as well as any other functions multiplexed to
those pins. Setting the bit enables the I/O ports and
other functions, but allows the interface to override
everything else on the pins when an external memory
operation is required. By default, the external bus is
always enabled and disables all other I/O.
The operation of the EBDIS bit is also influenced by the
program memory mode being used. This is discussed
in more detail in Section 7.5 “Program Memory
Modes and the External Memory Bus”.
REGISTER 7-1:
DS39778D-page 100
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-4
bit 3-2
bit 1-0
EBDIS
R/W-0
External Memory Bus Control
EBDIS: External Bus Disable bit
1 = External bus enabled when microcontroller accesses external memory; otherwise, all external bus
0 = External bus always enabled, I/O ports are disabled
Unimplemented: Read as ‘0’
WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits
11 = Table reads and writes will wait 0 T
10 = Table reads and writes will wait 1 T
01 = Table reads and writes will wait 2 T
00 = Table reads and writes will wait 3 T
Unimplemented: Read as ‘0’
WM1:WM0: TBLWT Operation with 16-Bit Data Bus Width Select bits
1x = Word Write mode: TABLAT word output, WRH active when TABLAT written
01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB) will activate
00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
drivers are mapped as I/O ports
U-0
—
MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
WAIT1
R/W-0
WAIT0
R/W-0
CY
CY
CY
CY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
The WAIT bits allow for the addition of wait states to
external memory operations. The use of these bits is
discussed in Section 7.3 “Wait States”.
The WM bits select the particular operating mode used
when the bus is operating in 16-Bit Data Width mode.
These are discussed in more detail in Section 7.6
“16-Bit Data Width Modes”. These bits have no effect
when an 8-bit Data Width mode is selected.
The MEMCON register (see Register 7-1) shares the
same memory space as the PR2 register and can be
alternately selected based on the designation of the
ADSHR
Register 24-9).
U-0
—
bit
U-0
in
—
the
© 2009 Microchip Technology Inc.
x = Bit is unknown
WDTCON
R/W-0
WM1
register
R/W-0
WM0
bit 0
(see
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