PIC18LF45K22-I/PT Microchip Technology, PIC18LF45K22-I/PT Datasheet - Page 244
![MCU 8BIT 32KB FLASH 3.6V 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF45K22-I/PT
Manufacturer Part Number
PIC18LF45K22-I/PT
Description
MCU 8BIT 32KB FLASH 3.6V 44TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF45K22-I/PT
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 30x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
1536Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 28 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF45K22-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18(L)F2X/4XK22
15.6.7
Master mode reception is enabled by programming the
Receive Enable bit, RCEN, of the SSPxCON2 register.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCLx pin changes (high-to-low/
low-to-high) and data is shifted into the SSPxSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPxSR are loaded into the SSPxBUF, the BF flag bit
is set, the SSPxIF flag bit is set and the Baud Rate
Generator is suspended from counting, holding SCLx
low. The MSSPx is now in Idle state awaiting the next
command. When the buffer is read by the CPU, the BF
flag bit is automatically cleared. The user can then
send an Acknowledge bit at the end of reception by set-
ting the Acknowledge Sequence Enable bit, ACKEN, of
the SSPxCON2 register.
15.6.7.1
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
15.6.7.2
In receive operation, the SSPxOV bit is set when 8 bits
are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
15.6.7.3
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
DS41412D-page 244
Note:
I
The MSSPx module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
2
C MASTER MODE RECEPTION
BF Status Flag
SSPxOV Status Flag
WCOL Status Flag
Preliminary
15.6.7.4 Typical Receive Sequence:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Master clears SSPxIF and reads the received
11. Master sets ACK value sent to slave in ACKDT
12. Masters ACK is clocked out to the slave and
13. User clears SSPxIF.
14. Steps 8-13 are repeated for each received byte
15. Master sends a not ACK or Stop to end
The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
SSPxIF is set by hardware on completion of the
Start.
SSPxIF is cleared by software.
User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
Address is shifted out the SDAx pin until all 8
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
The MSSPx module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
The MSSPx module generates an interrupt at
the end of the ninth clock cycle by setting the
SSPxIF bit.
User sets the RCEN bit of the SSPxCON2 regis-
ter and the Master clocks in a byte from the slave.
After the 8th falling edge of SCLx, SSPxIF and
BF are set.
byte from SSPxUF, clears BF.
bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
SSPxIF is set.
from the slave.
communication.
2010 Microchip Technology Inc.
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