PIC18F44J11-I/PT Microchip Technology, PIC18F44J11-I/PT Datasheet - Page 2
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PIC18F44J11-I/PT
Manufacturer Part Number
PIC18F44J11-I/PT
Description
IC PIC MCU FLASH 16KB 44-TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
Specifications of PIC18F44J11-I/PT
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
22
Ram Memory Size
3.6875KB
Cpu Speed
48MHz
No. Of Timers
5
No. Of Pwm Channels
2
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F44J11-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F46J11 FAMILY
TABLE 2:
DS80435H-page 2
MSSP
MSSP
EUSART
A/D
PMP
Low Power
DC
Characteristics
Special
Features
MSSP
A/D
CTMU
A/D Converter
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY
I
Mode
I
Reception
Enable/
Disable
F
Clock
PSP/PMP
Deep Sleep
Supply
Voltage
T1DIG
Port 1
Band Gap
Reference
Constant
Current
Sample
Acquisition
2
2
OSC
C™
C Slave
Feature
/2
Number
Item
10.
12.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
If a Stop condition occurs in the middle of an
address or data reception, there will be
issues with the SCL clock stream and RCEN
bit.
In I
problems receiving correct data.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 T
delay.
F
linearity error limits.
The data bus may not work correctly.
Wake-up events that occur during Deep
Sleep entry may not generate an event.
Minimum operating voltage (V
“F” devices is 2.25V.
T1DIG Configuration bit is not implemented.
When MSSP1 is in I
RB5 pins may have extraneous pulses.
At high V
conversion on Channel 15 could have
issues.
V
can cause the constant current source to
turn off.
ANx pin may output pull-up pulse during
acquisition.
OSC
DD
2
C slave reception, the module may have
voltages below the LVDSTAT threshold
/2 A/D Conversion mode may not meet
DD
voltages, performing an A/D
Issue Summary
2
C mode, the RB4 and
DD
) parameter
CY
2010 Microchip Technology Inc.
Affected Revisions
A2
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
(1)