ATTINY85-15ST1 Atmel, ATTINY85-15ST1 Datasheet - Page 77
![MCU AVR 8K FLASH 15MHZ 8-SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY85-15ST1
Manufacturer Part Number
ATTINY85-15ST1
Description
MCU AVR 8K FLASH 15MHZ 8-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-15MZ.pdf
(196 pages)
Specifications of ATTINY85-15ST1
Package / Case
8-SOIC (3.9mm Width)
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 105°C
Speed
16MHz
Number Of I /o
6
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
512 x 8
Program Memory Size
8KB (8K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.8.5
12.8.6
12.8.7
7598H–AVR–07/09
Output Compare Register B – OCR0B
Timer/Counter Interrupt Mask Register – TIMSK
Timer/Counter 0 Interrupt Flag Register – TIFR
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
• Bits 7..4, 0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
• Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
• Bits 7, 0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R
7
–
0
R
7
0
7
–
0
OCIE1A
OCF1A
R/W
R/W
6
R
0
6
0
6
0
OCIE1B
OCF1B
R/W
R/W
R
5
0
5
0
5
0
OCIE0A
OCF0A
R/W
R/W
R
4
0
4
0
4
0
OCR0B[7:0]
OCIE0B
OCF0B
R/W
R/W
R/W
3
0
3
0
3
0
TOIE1
TOV1
R/W
R/W
R/W
2
0
2
0
2
0
ATtiny25/45/85
TOIE0
TOV0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R
0
0
0
–
0
R
0
–
0
OCR0B
TIMSK
TIFR
77
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