PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 403

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

INDEX
A
A/D ................................................................................... 271
Absolute Maximum Ratings ............................................. 359
AC (Timing) Characteristics ............................................. 374
ACKSTAT ........................................................................ 225
ACKSTAT Status Flag ..................................................... 225
ADCAL Bit ........................................................................ 279
ADCON0 Register ............................................................ 271
ADCON1 Register ............................................................ 271
ADCON2 Register ............................................................ 271
ADDFSR .......................................................................... 348
ADDLW ............................................................................ 311
Addressable Universal Synchronous Asynchronous
ADDULNK ........................................................................ 348
ADDWF ............................................................................ 311
ADDWFC ......................................................................... 312
ADRESH Register ............................................................ 271
ADRESL Register .................................................... 271, 274
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 312
ANDWF ............................................................................ 313
Assembler
AUSART
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A/D Converter Interrupt, Configuring ....................... 275
Acquisition Requirements ........................................ 276
ADCAL Bit ................................................................ 279
ADCON0 Register .................................................... 271
ADCON1 Register .................................................... 271
ADCON2 Register .................................................... 271
ADRESH Register ............................................ 271, 274
ADRESL Register .................................................... 271
Analog Port Pins, Configuring .................................. 277
Associated Registers ............................................... 279
Automatic Acquisition Time ...................................... 277
Calibration ................................................................ 279
Configuring the Module ............................................ 275
Conversion Clock (T
Conversion Requirements ....................................... 392
Conversion Status (GO/DONE Bit) .......................... 274
Conversions ............................................................. 278
Converter Characteristics ........................................ 391
Operation in Power-Managed Modes ...................... 279
Special Event Trigger (CCP) .................................... 278
Use of the CCP2 Trigger .......................................... 278
Load Conditions for Device Timing
Parameter Symbology ............................................. 374
Temperature and Voltage Specifications ................. 375
Timing Conditions .................................................... 375
GO/DONE Bit ........................................................... 274
Receiver Transmitter (AUSART). See AUSART.
MPASM Assembler .................................................. 356
Asynchronous Mode ................................................ 262
Specifications ................................................... 375
Associated Registers, Receive ........................ 265
Associated Registers, Transmit ....................... 263
Receiver ........................................................... 264
Setting up 9-Bit Mode with Address Detect ..... 264
Transmitter ....................................................... 262
AD
) ........................................... 277
PIC18F85J90 FAMILY
Auto-Wake-up on Sync Break Character ......................... 249
B
Baud Rate Generator ...................................................... 221
BC .................................................................................... 313
BCF ................................................................................. 314
BF .................................................................................... 225
BF Status Flag ................................................................. 225
Bias Generation (LCD)
Block Diagrams
Baud Rate Generator (BRG) ................................... 260
Synchronous Master Mode ...................................... 266
Synchronous Slave Mode ........................................ 269
Charge Pump Design Considerations ..................... 173
A/D ........................................................................... 274
Analog Input Model .................................................. 275
AUSART Receive .................................................... 264
AUSART Transmit ................................................... 262
Baud Rate Generator .............................................. 221
Capture Mode Operation ......................................... 156
Comparator Analog Input Model .............................. 285
Comparator I/O Operating Modes ........................... 282
Comparator Output .................................................. 284
Comparator Voltage Reference ............................... 288
Comparator Voltage Reference Output
Compare Mode Operation ....................................... 157
Connections for On-Chip Voltage Regulator ........... 299
Device Clock .............................................................. 35
EUSART Receive .................................................... 247
EUSART Transmit ................................................... 245
External Power-on Reset Circuit
Fail-Safe Clock Monitor ........................................... 301
Generic I/O Port Operation ...................................... 115
Interrupt Logic .......................................................... 100
LCD Clock Generation ............................................. 168
LCD Driver Module .................................................. 163
LCD Regulator Connections (M0 and M1) .............. 170
MSSP (I
MSSP (I
MSSP (SPI Mode) ................................................... 191
On-Chip Reset Circuit ................................................ 51
PIC18F6XJ90 ............................................................ 12
PIC18F8XJ90 ............................................................ 13
PLL ............................................................................ 40
PWM Operation (Simplified) .................................... 159
Associated Registers ....................................... 260
Baud Rate Error, Calculating ........................... 260
Baud Rates, Asynchronous Modes ................. 261
High Baud Rate Select (BRGH Bit) ................. 260
Operation in Power-Managed Modes .............. 260
Sampling ......................................................... 260
Associated Registers, Receive ........................ 268
Associated Registers, Transmit ....................... 267
Reception ........................................................ 268
Transmission ................................................... 266
Associated Registers, Receive ........................ 270
Associated Registers, Transmit ....................... 269
Reception ........................................................ 270
Transmission ................................................... 269
Buffer Example ................................................ 289
(Slow V
2
2
C Master Mode) ........................................ 219
C Mode) .................................................... 200
DD
Power-up) ........................................ 53
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