PIC18F25J50-I/SP Microchip Technology, PIC18F25J50-I/SP Datasheet - Page 170
![IC PIC MCU FLASH 32K 2V 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F25J50-I/SP
Manufacturer Part Number
PIC18F25J50-I/SP
Description
IC PIC MCU FLASH 32K 2V 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
4.PIC18F24J50-ISS.pdf
(18 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F25J50-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART/I2C/SPI
Maximum Clock Frequency
48 MHz
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180024
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25J50-I/SP
Manufacturer:
MICROCHIP
Quantity:
1 001
- PIC18LF24J10-ISS PDF datasheet
- PIC18LF24J50-ISS PDF datasheet #2
- PIC18LF24J50-ISS PDF datasheet #3
- PIC18F24J50-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 170 of 430
- Download datasheet (7Mb)
PIC18F2XK20/4XK20
15.1
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
FIGURE 15-1:
DS41303D-page 168
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Timer3 Operation
T1OSI
CCP1/CCP2 Select from T3CON<6,3>
CCP1/CCP2 Special Event Trigger
Timer1 Oscillator
TIMER3 BLOCK DIAGRAM
T1OSCEN
T3CKPS<1:0>
T3SYNC
TMR3ON
(1)
TMR3CS
Internal
Clock
F
OSC
/4
Preliminary
1
0
Timer1 Clock Input
Clear TMR3
Prescaler
1, 2, 4, 8
The operating mode is determined by the clock select
bit, TMR3CS of the T3CON register. When TMR3CS is
cleared (= 0), Timer3 increments on every internal
instruction cycle (F
increments on every rising edge of the Timer1 external
clock input or the Timer1 oscillator, if enabled.
As with Timer1, the digital circuitry associated with the
RC1/T1OSI and RC0/T1OSO/T13CKI pins is disabled
when the Timer1 oscillator is enabled. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
2
TMR3L
Sleep Input
Synchronize
OSC
Detect
High Byte
/4). When the bit is set, Timer3
TMR3
© 2008 Microchip Technology Inc.
1
0
on Overflow
TMR3IF
Set
Timer3
On/Off
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