PIC16F83-04/SO Microchip Technology, PIC16F83-04/SO Datasheet - Page 659

• Manufacturer Part Number: PIC16F83-04/SO
• Description: IC MCU FLASH 512X14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F83-04/SO

• Core Size: 8-Bit
• Program Memory Size: 896B (512 x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 36Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 36 B
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

Transfer direction of data and acknowledgment bits depends on R/W bits.
Sr
Combined format - A master addresses a slave with a 10-bit address, then transmits
1997 Microchip Technology Inc.
Combined format:
S
(Code + A9:A8)
Slave Address
From slave to master
From master to slave
Slave Address R/W A Data A/A Sr
(write)
(read)
R/W A
data to this slave and reads data from this slave.
When a master does not wish to relinquish the bus (which occurs by generating a STOP condi-
tion), a repeated START condition (Sr) must be generated. This condition is identical to the start
condition (SDA goes high-to-low while SCL is high), but occurs after a data transfer acknowledge
pulse (not the bus-free state). This allows a master to send “commands” to the slave and then
receive the requested information or to address a different slave device. This sequence is shown
in
Figure A-8:
Figure
Slave Address
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(A7:A0)
A-8.
Sr = repeated
Start Condition
(n bytes + acknowledge)
(read or write)
Combined Format
Slave Address R/W A Data A/A
A
Data
A
(write)
Data A/A
Direction of transfer
may change at this point
Sr Slave Address
(Code + A9:A8)
P
(read)
Appendix A
R/W A Data A
DS31034A-page 34-7
Data
A P
34