PIC24FJ32GA102-I/SO Microchip Technology, PIC24FJ32GA102-I/SO Datasheet - Page 2

• Manufacturer Part Number: PIC24FJ32GA102-I/SO
• Description: IC MCU 16BIT 32KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA102-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (11K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001, MA240020, DM240002, DM240011, DV164033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GA104
TABLE 2:
DS80486E-page 2
Output
Compare
UART
Oscillator
SPI
SPI
Triple
(Enhanced)
Comparator
Core
A/D Converter
Interrupts
Oscillator
A/D Converter
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
Cascaded
mode
Break
Character
Generation
Secondary
Oscillator
Configuration
Master mode
Master mode
Doze Mode
INTx
SILICON ISSUE SUMMARY
Feature
—
—
—
—
Number
Item
10.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Cascaded mode does not work as expected.
Will not generate back-to-back Break characters.
High-current draw when external signal applied under
certain conditions.
Spurious transmission and reception of null data on wake-up
from Sleep (Master mode).
Inaccurate SPITBF flag with high clock divider.
No interrupt generation with internal band gap reference.
Instruction execution glitches following DOZE bit changes.
Disabled voltage references during Debug mode.
External interrupts missed when writing to INTCON2.
POSCEN bit does not work with Primary + PLL modes
Module continues to draw current when disabled.
Issue Summary
 2010 Microchip Technology Inc.
Revisions
Affected
A2
X
X
X
X
X
X
X
X
X
X
X
(1)