PIC16F84AT-04I/SO Microchip Technology, PIC16F84AT-04I/SO Datasheet - Page 106
![IC MCU FLASH 1KX14 EE 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F84AT-04I/SO
Manufacturer Part Number
PIC16F84AT-04I/SO
Description
IC MCU FLASH 1KX14 EE 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84AT-04I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
For Use With
I3-DB16F84A - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F84AT-04I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 106 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
6.3.4
DS31006A-page 6-12
Indirect Addressing, INDF, and FSR Registers
Indirect addressing is a mode of addressing data memory where the data memory address in
the instruction is not fixed. An SFR register is used as a pointer to the data memory location that
is to be read or written. Since this pointer is in RAM, the contents can be modified by the pro-
gram. This can be useful for data tables in the data memory.
indirect addressing. This shows the moving of the value to the data memory address specified
by the value of the FSR register.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register
actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF reg-
ister itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a
no-operation (although status bits may be affected). An effective 9-bit address is generated by
the concatenation of the IRP bit (STATUS<7>) with the 8-bit FSR register, as shown in
Figure 6-7: Indirect Addressing
Instruction
Executed
Instruction
Fetched
Opcode
Opcode
Address != 0
RP1:RP0
2
Address
File
9
7
9
Address = 0h
File Address = INDF
IRP
9
Figure 6-7
FSR
RAM
1997 Microchip Technology Inc.
shows the operation of
Figure
6-8.
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