PIC16LC642-04/SP Microchip Technology, PIC16LC642-04/SP Datasheet - Page 25

• Manufacturer Part Number: PIC16LC642-04/SP
• Description: IC MCU OTP 4KX14 COMP 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC642-04/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Interface Type: RS- 232
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

4.2.2.5
This register contains the individual flag bits for the
comparator and Parallel Slave Port interrupts.
FIGURE 4-9:
1996 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5-0: Unimplemented: Read as '0'
Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.
PSPIF
R/W-0
(1)
PIR1 REGISTER
PSPIF
1 = A read or write operation has taken place (must be cleared in software)
0 = No read or write operation has taken place
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
R/W-0
CMIF
PIR1 REGISTER (ADDRESS 0Ch)
(1)
: Parallel Slave Port Interrupt Flag bit
U-0
—
U-0
—
U-0
—
Preliminary
PIC16C64X & PIC16C66X
U-0
—
Note:
U-0
—
bit0
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
U-0
—
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
DS30559A-page 25