PIC16F871T-I/PT Microchip Technology, PIC16F871T-I/PT Datasheet - Page 326
![IC MCU FLASH 2KX14 EE 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16F871T-I/PT
Manufacturer Part Number
PIC16F871T-I/PT
Description
IC MCU FLASH 2KX14 EE 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F870-ISO.pdf
(172 pages)
4.PIC16F870-ISO.pdf
(6 pages)
Specifications of PIC16F871T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
PSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
28 bit
For Use With
I3-DB16F871 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F871T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F870-ISO PDF datasheet #3
- PIC16F870-ISO PDF datasheet #4
- Current page: 326 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.18.1 Bus Collision During a START Condition
DS31017A-page 17-50
During a START condition, a bus collision occurs if:
a)
b)
During a START condition both the SDA and the SCL pins are monitored.
If:
then:
The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sam-
pled high, the baud rate generator is loaded from SSPADD<6:0> and counts down to 0. If the
SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that
another master is attempting to drive a data '1' during the START condition.
If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted
early
the end of the BRG count. The baud rate generator is then reloaded and counts down to 0, and
during this time, if the SCL pins is sampled as '0', a bus collision does not occur. At the end of
the BRG count the SCL pin is asserted low.
Note:
SDA or SCL are sampled low at the beginning of the START condition
SCL is sampled low before SDA is asserted low
the SDA pin is already low
or the SCL pin is already low,
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure
The reason that bus collision is not a factor during a START condition is that no two
bus masters can assert a START condition at the exact same time. Therefore, one
master will always assert SDA before the other. This condition does not cause a bus
collision because the two masters must be allowed to arbitrate the first address fol-
lowing the START condition, and if the address is the same, arbitration must be
allowed to continue into the data portion, Repeated Start, or STOP conditions.
17-37). If however a '1' is sampled on the SDA pin, the SDA pin is asserted low at
Preliminary
(Figure
(Figure
17-35).
17-36).
1997 Microchip Technology Inc.
(Figure
17-35).
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