AT32UC3L064-ZAUT Atmel, AT32UC3L064-ZAUT Datasheet - Page 828
![IC MCU AVR32 64KB FLASH 48VQFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3L064-ZAUT
Manufacturer Part Number
AT32UC3L064-ZAUT
Description
IC MCU AVR32 64KB FLASH 48VQFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3L-EK.pdf
(858 pages)
Specifications of AT32UC3L064-ZAUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (13Mb)
35.2.9
35.2.10
35.2.11
32099F–11/2010
TWI
PWMA
CAT
5. SPI mode fault detection enable causes incorrect behavior
1. TWIM.SR.IDLE goes high immediately when NAK is received
2. TWIM SMBAL polarity is wrong
1. BUSY bit is never cleared after writes to the Control Register (CR)
2. Incoming peripheral events are discarded during duty cycle register update
1. CAT asynchronous wake will be delayed by one AST peripheral event period
reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer,
the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is
empty, and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer,
enable the SPI and the PDCA.
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
The SMBAL signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the SMBAL cannot be used.
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA clock
period when an incoming peripheral event is expected.
AT32UC3L016/32/64
828
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