DSPIC33FJ16MC304-I/PT Microchip Technology, DSPIC33FJ16MC304-I/PT Datasheet - Page 7

• Manufacturer Part Number: DSPIC33FJ16MC304-I/PT
• Description: IC DSPIC MCU/DSP 16K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 35
• Flash Memory Size: 16KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17. Module: I
18. Module: I
19. Module: I
© 2010 Microchip Technology Inc.
With the I
external
associated with the SCL and SDA pins do not
reflect the actual digital logic levels on the pins.
Work around
If the SDA and/or SCL pins need to be polled,
these pins should be connected to other port pins
in order to be read correctly. This issue does not
affect the operation of the I
Affected Silicon Revisions
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register I2CxRCV, if the lower address
byte
particular, these include all addresses with the
form XX0000XXXX and XX1111XXXX, with the
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
Affected Silicon Revisions
When the I
or Slave mode, after the ACKSTAT bit is set when
receiving a NACK, it may be cleared by the
reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK.
Affected Silicon Revisions
A2
A2
A2
X
X
X
matches
A3
A3
A3
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
X
X
X
2
interrupt
C module enabled, the PORT bits and
2
2
2
2
C module is operating in either Master
C
C
C
A4
A4
A4
X
X
X
the
A5
A5
A5
X
X
X
input
reserved
A6
A6
A6
2
X
X
X
C module.
functions
addresses.
(if
any)
In
20. Module: CPU
21. Module: PWM
22. Module: PWM
The EXCH instruction does not execute correctly.
Work around
If
recommended work around is to replace:
EXCH Wsource, Wdestination
with:
PUSH Wdestination
MOV Wsource, Wdestination
POP Wsource
If using the MPLAB C30 C compiler, specify the
compiler option: -merrata=exch (Project > Build
Options > Projects > MPLAB C30 > Use Alternate
Settings).
Affected Silicon Revisions
If the PTDIR bit is set (when PTMR is counting
down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
up, as if PTDIR was zero.
Work around
None.
Affected Silicon Revisions
When the device is operated in DOZE mode and
the Motor Control PWM module has a postscaler
set to any value different than 1:1 (PTOPS > 0 in
PxTCON register), the Motor Control PWM
module generates more interrupts than expected.
Work around
Do not use DOZE mode with the Motor Control
PWM if the time base output postscaler is different
than 1:1 (PTOPS > 0 in PxTCON register).
Affected Silicon Revisions
A2
A2
A2
X
X
X
writing
A3
A3
A3
X
X
X
source
A4
A4
A4
X
X
X
A5
A5
A5
X
X
X
code
A6
A6
A6
X
X
X
in
DS80463E-page 7
assembly,
the