PIC24FJ64GA004-I/ML Microchip Technology, PIC24FJ64GA004-I/ML Datasheet - Page 9

• Manufacturer Part Number: PIC24FJ64GA004-I/ML
• Description: IC PIC MCU FLASH 21KX24 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA004-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 44-QFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM300027, DV164033, MA240013, AC164127, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 35
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2006 Microchip Technology Inc.
Section 30. Programmable Cyclic Redundancy Check (CRC)
30.5.2.2
The number of data bits to be shifted depends upon the length of the polynomial selected. For
example, if PLEN<3:0> = 5, then the length of the generator polynomial and the size of one data
is 6 bits (PLEN<3:0> + 1). In this case, a full byte of a FIFO location is not shifted out, even
though the CPU can write only a byte. Only 6 bits of a byte are shifted out, starting from the 6th
bit (i.e., the MSb in this case). The two Most Significant bits of each byte are don’t care bits.
Therefore, for a given value of PLEN3:PLEN0, it will take ((PLEN<3:0> + 1) * VWORD) number
of shift clock cycles to complete the CRC calculations. Similarly, for a 12-bit polynomial selection,
the shifting starts from the 12th bit of the word, which is the Most Significant bit for this selection.
The Most Significant 4 bits of each word are ignored.
30.5.2.3
When the CPU reads the CRCWDAT register, the CRC result is read directly out of the shift
register through the CRC read bus. To get the correct CRC reading, it is necessary to wait for the
CRCMPT bit to go high before reading the CRCWDAT register.
A direct write path to the CRC Shift registers is also provided through the CRC write bus. This
path is accessed by the CPU through the CRCWDAT register. The CRCWDAT register can be
loaded with a desired value prior to the start of the shift process.
30.5.3
Serial shifting of the FIFO data to the CRC engine begins when the CRCGO bit is set and the
VWORD4:VWORD0 bits (VWORD) are greater than zero. During this process, if the CRCMPT
bit makes a transition from ‘0’ (not empty) to ‘1’ (empty), or when the VWORD4:VWORD0 bits
make a transition from any value greater than zero to zero, the CRCIF interrupt flag becomes
set. If the CRC interrupt is enabled by setting the CRCIE bit, and the CRCIF bit becomes set,
then an interrupt is generated.
Table 30-2 in Section 30.9 “Register Maps” details the interrupt register associated with the CRC
module. For more details on interrupts and interrupt priority settings, refer to Section 8. “Interrupts”.
Note:
Note:
Note:
NUMBER OF DATA BITS SHIFTED FROM FIFO
CRC RESULT
Interrupt Operation
For ‘n’ bit polynomial selection, the CRC calculation is done with integer multiple of
‘n’ bit of data. For example, for a 16 bit polynomial, the CRC calculation is done with
integer multiple of words.
When the CPU writes the shift registers directly though the CRCWDAT register, the
CRCGO bit must be ‘0’.
If new data is written into the CRCDAT register when the CRCFUL bit is set, the
VWORD Pointer rolls over through ‘0’. However, the CRC Interrupt Flag, CRCIF, is
not set in this condition. In this condition, the CRCFUL bit gets reset, all previous
data written into the FIFO is lost and the new data is written into the first location of
the FIFO. Remaining locations of the FIFO are empty and new data can be written
into the empty locations.
Advance Information
DS39714A-page 30-9
30