PIC16F73-I/ML Microchip Technology, PIC16F73-I/ML Datasheet - Page 109

• Manufacturer Part Number: PIC16F73-I/ML
• Description: IC MCU FLASH 4KX14 A/D 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F73-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of Pwm: RoHS Compliant
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16F73I/ML

1997 Microchip Technology Inc.
Example 6-4: RAM Initialization
Bank0_LP
;
; Next Bank (Bank1)
; (** ONLY REQUIRED IF DEVICE HAS A BANK1 **)
;
Bank1_LP
;
; Next Bank (Bank2)
; (** ONLY REQUIRED IF DEVICE HAS A BANK2 **)
;
Bank2_LP
;
; Next Bank (Bank3)
; (** ONLY REQUIRED IF DEVICE HAS A BANK3 **)
;
Bank3_LP
:
CLRF
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
BSF
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
Section 6. Memory Organization
STATUS
0x20
FSR
INDF0
FSR
FSR, 7
Bank0_LP
0xA0
FSR
INDF0
FSR
STATUS, C
Bank1_LP
STATUS, IRP
0x20
FSR
INDF0
FSR
FSR, 7
Bank2_LP
0xA0
FSR
INDF0
FSR
STATUS, C
Bank3_LP
; Clear STATUS register (Bank0)
; 1st address (in bank) of GPR area
; Move it to Indirect address register
; Clear GPR at address pointed to by FSR
; Next GPR (RAM) address
; End of current bank ? (FSR = 80h, C = 0)
; NO, clear next location
; 1st address (in bank) of GPR area
; Move it to Indirect address register
; Clear GPR at address pointed to by FSR
; Next GPR (RAM) address
; End of current bank? (FSR = 00h, C = 1)
; NO, clear next location
; Select Bank2 and Bank3
;
; 1st address (in bank) of GPR area
; Move it to Indirect address register
; Clear GPR at address pointed to by FSR
; Next GPR (RAM) address
; End of current bank? (FSR = 80h, C = 0)
; NO, clear next location
; 1st address (in bank) of GPR area
; Move it to Indirect address register
; Clear GPR at address pointed to by FSR
; Next GPR (RAM) address
; End of current bank? (FSR = 00h, C = 1)
; NO, clear next location
; YES, All GPRs (RAM) is cleared
for Indirect addressing
DS31006A-page 6-15
6